The power factor (PF) at the input port of a circuit is a parameter that is related to a ratio between the amount of real power drawn by the circuit (e.g., the average power entering the input port of the circuit) and the amount of apparent power drawn by the circuit (e.g., the product of the root-mean-square, or RMS, voltage at the input port and the RMS current at the input port). In an ac-dc converter, high power factor is generally desired to best convey real power from an alternating current (ac) input to a direct current (dc) output. For example, in a power converter used as a grid interface, a high PF is desired to maintain high power quality. A common technique to achieve high power factor is to cascade a “Power Factor Correction” (PFC) rectifier circuit with a de-dc converter. The PFC circuit shapes a sinusoidal input current and buffers twice-line-frequency ac power on a capacitor with a certain average do voltage. The subsequent dc-dc converter then regulates the load voltage from this buffered voltage.
A boost converter is often selected for use in a PFC circuit because of its high power factor capability (about 0.99). However, a boost converter will typically require the use of high-voltage rated switch, diode, and capacitor components (e.g., 2-3 times peak voltage of about 200-400V). Even worse, in the case of a low do voltage load application, the subsequent dc-dc converter would need a high step-down conversion ratio from the high stepped-up buffered voltage to the low do voltage. Therefore, high voltage stress will exist on the components of the dc-dc converter, deteriorating the efficiency.
Instead of a boost converter, one alternative for a PFC circuit is a buck converter, which draws a clipped current waveform (i.e., draws current when the input ac voltage magnitude exceeds the do buffer voltage). Often a clipped-sine current waveform is drawn, yielding a ˜0.9-0.95 power factor for typical ac inputs. A benefit of a PFC having a buck topology is the reduced voltage stress and conversion ratio for the corresponding dc-dc converter. However, the active components in the buck PFC circuit still need to be operated directly from the ac line voltage, and thus the buck PFC needs to be designed with high voltage (e.g., 300-600V) active devices. This high voltage requirement also typically results in low achievable switching frequencies and the need for large passive components. Moreover, in both typical boost and buck PFC circuits, the twice-line frequency energy is stored on an output capacitor with small twice-line-frequency voltage ripple, requiring a peak capacitive energy storage rating that is large compared to the amount of twice-line-frequency energy that needs to be buffered. Consequently, PFC circuits with buck converters often display low efficiency and low power density.
New power conversion architectures and methods are needed that are capable of achieving high power factor with one or more of high switching frequency, low component voltage stress, low buffer energy storage requirements, high power density, and/or high efficiency.